1. Field of the Invention
The field of the invention relates to interconnect structures for input and output signals of an integrated circuit. More specifically, the present invention relates to the interconnect structure for programmable logic devices.
2. Background Technology
Integrated circuits (ICs), and specifically programmable ICs such as field programmable gate arrays (FPGAs), contain a number of input and output signal pads. When packaged, these pads are coupled through leads to external pins that are used to connect the IC to a larger system or "board" that contains other ICs. When packaged with pins, the IC is often called a "chip" or IC chip.
A system designer conventionally develops a particular board layout giving particular assignments for both the chips of the board and for the signal lines that run between the chips. Therefore, based on the particular socket or area on the board where a chip is to sit, a designer predetermines which input/output signals are to be assigned to which input/output pins of the chip. This pin assignment is often performed before the chip is designed or before the design is laid-out in the IC. Once assigned, a pin is said to be "locked" from use by other signals. As discussed below, IC pin "lock" can cause severe problems for a circuit designer in terms of circuit layout.
FIG. 1 illustrates a typical FPGA 50 including a number of configurable logic blocks (CLBs) 20 that are coupled to a programmable interconnect structure (not shown). As is well known, the interconnect structure allows input/output lines of CLBs 20 to be programmably coupled together. CLBs 20, also well known, can be programmed to perform a number of different logic functions.
FPGA 50 also contains a number of input/output blocks (IOBs) 32 that are used by the IC as an interface between external pins 12 and CLBs 20. IOBs 32 are similarly coupled to the programmable interconnect structure. Although CLBs 20 are coupled together using the programmable interconnect structure, each IOB 32 is directly coupled to an individual pad 10 and an individual external pin 12. For example, IOB 32a of FIG. 1 is directly coupled to pad 10a having an external pin 12a.
As discussed above, when FPGA 50 is to be programmed, its pin assignments can be predetermined, i.e. certain signals are assigned to individual pins. However, when the circuit design to be programmed on FPGA 50 is being designed, it may be more efficient to place certain logic within one or more CLBs that are not spatially near the pin and associated IOB that are to output the signal generated by the logic. For instance, it may be more efficient or a better use of resources to have CLB 20a generate a signal that distant pin 12c needs even though these elements are not near each other. Alternatively, it may be more efficient or easier to place certain logic within one or more CLBs that are not spatially near the pin and associated IOB that input the signal needed by the certain logic. However, by placing the logic far away from its associated pin, a routing problem exists in supplying the signals from the logic to the pin.
A chip layout problem occurs as a result of the predetermined pin assignments done by system designers. Specifically, circuit layout designers feel constrained or forced to fit a large amount of circuitry into the area of FPGA 50 that is near the assigned pins. This design method is problematic because not all of the logic associated with a particular input or output pin can easily be placed adjacent to the pin. In some cases, there are not enough routing resources within the constrained IC area. Therefore, signal routing becomes a problem as the circuitry is spread out. In some instances, circuit design and functionality become reduced to fit in the constrained area. In other instances, the crowded circuits fit near the pins, but there is little room for additional circuits or expansion, thereby causing signal delays and/or signal errors because of indirect or complex signal routing.
In either of the above cases, it is more advantageous to uniformly utilize the resources of FPGA 50 that are distributed throughout the FPGA's area. Therefore, a need arises for a mechanism that allows system designers to evenly spread logic throughout FPGA 50 device even though the pins of FPGA 50 device are preassigned ("locked"). The present invention allows such advantageous functionality.